View CA3078_183069.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CA3078, CA3078A
Data Sheet December 1998 File Number 535.5
2MHz, Micropower Operational Amplifier
The CA3078 and CA3078A are high gain monolithic operational amplifiers which can deliver milliamperes of current yet only consume microwatts of standby power. Their operating points are externally adjustable and frequency compensation may be accomplished with one external capacitor. The CA3078 and CA3078A provide the designer with the opportunity to tailor the frequency response and improve the slew rate without sacrificing power. Operation with a single 1.5V battery is a practical reality with these devices. The CA3078A is a premium device having a supply voltage range of V = 0.75V to V = 15V. The CA3078 has the same lower supply voltage limit but the upper limit is V+ = +6V and V- = -6V.
Features
* Low Standby Power . . . . . . . . . . . . . . . As Low As 700nW * Wide Supply Voltage Range. . . . . . . . . . . 0.75V to 15V * High Peak Output Current . . . . . . . . . . . . . . . 6.5mA (Min) * Adjustable Quiescent Current * Output Short Circuit Protection
Applications
* Portable Electronics * Telemetry * Medical Electronics * Intrusion Alarms * Instrumentation
Pinouts
CA3078 (PDIP, SOIC) TOP VIEW
Ordering Information
PART NUMBER TEMP. (BRAND) RANGE (oC) CA3078AE CA3078AM (3078A) CA3078AM96 (3078A) CA3078AT CA3078E CA3078M (3078) CA3078T -55 to 125 -55 to 125 -55 to 125 -55 to 125 0 to 70 0 to 70 0 to 70 PACKAGE 8 Ld PDIP 8 Ld SOIC PKG. NO. E8.3 M8.15
COMP 1 INV. INPUT 2 NON-INV. 3 INPUT V- 4 +
8 COMP
-
7 V+ 6 OUTPUT 5 BIAS
8 Ld SOIC Tape and Reel M8.15 8 Pin Metal Can 8 Ld PDIP 8 Ld SOIC 8 Pin Metal Can T8.C E8.3 M8.15 T8.C
CA3078 (METAL CAN) TOP VIEW
COMP TAB 8 1 INV. 2 INPUT NON-INV. 3 INPUT + 5 4 V7 V+ 6 OUTPUT RSET V+
BIAS
NOTE: Case Voltage = Floating
Schematic Diagram
7 D2 D3 D5 Q10 Q6 Q4 NONINVERTING 3 Q1 Q3 INVERTING 2 BIAS 5 Q2 D1 D4 1 D9 D8 Q8 D6 Q5 D7 Q9 Q14 50 V4 Q7 Q11 Q13 Q15 Q17 Q16 OUTPUT 6 Q12 50 V+ Q18
COMPENSATION
8
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
CA3078, CA3078A
Absolute Maximum Ratings
Supply Voltage (Between V+ and V- Terminal) CA3078 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14V CA3078A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ to VInput Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.1mA Output Short Circuit Duration (Note 1). . . . . . . . . . . . . No Limitation
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 130 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 165 N/A Metal Can Package . . . . . . . . . . . . . . . 175 100 Maximum Junction Temperature (Metal Can Package). . . . . . . .175oC Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range CA3078 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CA3078A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Short circuit may be applied to ground or to either supply. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
For Equipment Design CA3078 LIMITS CA3078A LIMITS RSET = 5.1M TA = 0oC to 70oC MAX 4.5 32 170 130 1560 MIN 86 5 -5 to +5 6.5 MAX 5 40 200 150 1800 30 MIN 92 5.1 80 76 76 TA = 25oC TYP 0.70 0.50 7 100 20 240 5.3 -5.5 to +5.8 115 12 105 105 MAX 3.5 2.5 12 25 300 TA = -55oC to 125oC MIN 90 5 -5 to +5 6.5 MAX 4.5 5.0 50 45 540 30 UNITS mV nA nA dB A W V V dB mA V/V V/V
TEST CONDITIONS
RSET = 1M TA = 25oC MIN 88 5.1 80 76 76 TYP 1.3 6 60 92 100 1200 5.3 -5.5 to +5.8 110 12 93 93
PARAMETER VIO IIO IIB AOL IQ PD VOM VICR CMRR IOM+ or IOMVIO/V+ VIO/V-
V+ and V6V
RS (k) 10 10 10 10 10
RL (k) 10 10 -
RSET = 13M VIO AOL IQ PD VOM CMRR IIB IIO 15V 10 10 10 10 92 13.7 80 1.4 100 20 600 14.1 106 7 0.50 3.5 30 750 14 2.7 88 13.5 4.5 50 1350 55 5.5 mV dB A W V dB nA nA
2
CA3078, CA3078A
Electrical Specifications
TA = 25oC, Typical Values Intended Only for Design Guidance CA3078 V+ = +1.3V, V- = -1.3V RSET = 2M 1.3 1.7 9 80 10 26 1.4 -0.8 to +1.1 100 12 20 V+ = +0.75V, V- = -0.75V RSET = 10M 1.5 0.5 1.3 60 1 1.5 0.3 -0.2 to +0.5 90 0.5 50 V+ = +1.3V, V- = -1.3V RSET = 2M 0.7 0.3 3.7 84 10 26 1.4 -0.8 to +1.1 100 12 20 CA3078A V+ = +0.75V, V- = -0.75V RSET = 10M 0.9 0.054 0.45 65 1 1.5 0.3 -0.2 to +0.5 90 0.5 50
PARAMETER VIO IIO IIB AOL IQ PD VOP-P VICR CMRR IOM VIO/V
UNITS mV nA nA dB A W V V dB mA V/V
Electrical Specifications
PARAMETER VIO/TA IIO/TA GBWP SR
TA = 25oC and VSUPPLY = 6V, Typical Values Intended Only for Design Guidance CA3078 CA3078A RSET = 5.1M 5 6.3 0.3 0.027 0.5 3 7.4 1 40 0.25 RSET = 1M 6 70 2 0.04 1.5 2.5 1.7 0.8 UNITS V/oC pA/oC MHz V/s V/s s M k nV/Hz pA/Hz
TEST CONDITIONS RS 10k RS 10k AV = 100, C1 = 10pF See Figures 23, 24
RSET = 1M 6 70 2 0.04 1.5
tR RI RO eN(10Hz) iN(10Hz)
10% to 90% Rise Time RS = 0 RS = 1M
2.5 0.87 0.8 25 1
3
CA3078, CA3078A Test Circuits
V+ 100k V+ 0V 100k VIN R2 C2 3 51k 2 7 100k V+ 7 0V 6 8 1 4 VR1 OPTIONAL R2 - C2 COMP. R1 C1 R1 OPTIONAL R2 - C2 COMP. 10k CL R2 VOUT 0V VIN 100k 4 VR1 C1 C2 3 2 V+
RSET
RSET
CA3078 CA3078A +
5
CA3078 CA3078A + 1
5 0V 6 8 CL 10k VOUT
FIGURE 1. TRANSIENT RESPONSE AND SLEW RATE, UNITY GAIN (INVERTING) TEST CIRCUIT
NON-INVERTING V+ INPUT RI 3 7 + CA3078 CA3078A
FIGURE 2. SLEW RATE, UNITY GAIN (NON-INVERTING) TEST CIRCUIT
INVERTING RF INPUT V+ 7
OUTPUT 6 V+
RI
2
V+ RB 1M V2
CA3078 CA3078A OUTPUT 6
RF
4 1M VV-
RB 3
+
4 V-
RI
Value of RB required to have a null adjustment range of 7.5mV RI RF V+ RB (RI + RF) 7.5 x 10-3 assuming RB > > RI RF RI + RF
Value of RB required to have a null adjustment range of 7.5mV RI V+ RB 7.5 x 10-3 assuming RB > > RI
FIGURE 3. OFFSET VOLTAGE NULL CIRCUITS
5.1M 5.1M
10M 7 VP-P 1F 510k 2
RSET = 30M 5 6 + VP-P 1F RL 8 5F 1.5V "AA" CELL +
10M 7 2 510k 1F 3 10M + 1 4 7pF 8
RSET = 30M 5 6 + 5F RL 1.5V "AA" CELL +
CA3078 CA3078A
-
CA3078 CA3078A
-
3
+ 1 4 7pF
10M
FIGURE 4. INVERTING 20dB AMPLIFIER CIRCUIT
FIGURE 5. NON-INVERTING 20dB AMPLIFIER CIRCUIT
4
CA3078, CA3078A
TABLE 1. UNITY GAIN SLEW RATE vs COMPENSATION - CA3078 AND CA3078A VSUPPLY = 6V, Output Voltage (VO) = 5V, Load Resistance (RL) = 10k, Transient Response: 10% overshoot for an output voltage of 100mV, Ambient Temperature (TA) = 25oC UNITY GAIN (INVERTING) FIGURE 1 COMPENSATION TECHNIQUE CA3078 - IQ = 100A Single Capacitor Resistor and Capacitor Input CA3078A - IQ = 20A Single Capacitor Resistor and Capacitor Input 0 14 300 100 0 0 3.5 750 350 0 R1 k C1 pF R2 k C2 F SLEW RATE V/s R1 k UNITY GAIN (NON-INVERTING) FIGURE 2 C1 pF R2 k C2 F SLEW RATE V/s

0.25
0 0 0.306
0.0085 0.04 0.67
0 5.3
1500 500 0

0.311
0 0 0.45
0.0095 0.024 0.67

0.644
0 0 0.156
0.0095 0.027 0.29
0 34
800 125 0

0.77
0 0 0.4
0.003 0.02 0.4
Application Information
Compensation Techniques
The CA3078A and CA3078 can be phase compensated with one or two external components depending upon the closed loop gain, power consumption, and speed desired. The recommended compensation is a resistor in series with a capacitor connected from Terminal 1 to Terminal 8. Values of the resistor and capacitor required for compensation as a function of closed loop gain are shown in Figures 25 and 26. These curves represent the compensation necessary at quiescent currents of 100A and 20A, respectively, for a transient response with 10% overshoot. Figures 23 and 24 show the slew rates that can be obtained with the two different compensation techniques. Higher speeds can be achieved
with input compensation, but this increases noise output. Compensation can also be accomplished with a single capacitor connected from Terminal 1 to Terminal 8, with speed being sacrificed for simplicity. Table 1 gives an indication of slew rates that can be obtained with various compensation techniques at quiescent currents of 100A and 20A.
Single Supply Operation
The CA3078A and CA3078 can operate from a single supply with a minimum total supply voltage of 1.5V. Figures 4 and 5 show the CA3078A or CA3078 in inverting and non-inverting 20dB amplifier configurations utilizing a 1.5V type "AA" cell for a supply. The total consumption for either circuit is approximately 675nW. The output voltage swing in this configuration is 300mVP-P with a 20k load.
Typical Performance Curves
VS = 6 TA = 25oC RS 10k INPUT OFFSET VOLTAGE (mV) VS = 6 TA = 25oC
INPUT OFFSET CURRENT (nA)
10
CA3078 1 CA3078A 0.1
3.0 2.4 1.8 1.2 0.6 0 1 10 100 1000 TOTAL QUIESCENT CURRENT (A) CA3078 CA3078A
0.01 1 10 1000 100 TOTAL QUIESCENT CURRENT (A) 10000
FIGURE 6. INPUT OFFSET VOLTAGE vs TOTAL QUIESCENT CURRENT
FIGURE 7. INPUT OFFSET CURRENT vs TOTAL QUIESCENT CURRENT
5
CA3078, CA3078A Typical Performance Curves
VS = 6 TA = 25oC OPEN LOOP VOLTAGE GAIN (dB) 100 INPUT BIAS CURRENT (nA)
(Continued)
TA = 25oC CA3078A CA3078 126 RL = 1M 108 90 10k 2k 72 54 36 18 0 1 10 100 TOTAL QUIESCENT CURRENT (A) 1000 VS = 6 TO VS = 15 TA = 25oC 1 1 10 100 1000 TOTAL QUIESCENT CURRENT (A) VS = 6 IQ = 100A C1 = 10pF C1 = 30pF 100 300 1000 0 100 200 300 400 PHASE ANGLE (DEGREES) C1 = 0pF
10
CA3078 CA3078A
126 108 90 72 54 36 18 0
1
0.1 1 10 100 1000 10000 TOTAL QUIESCENT CURRENT (A)
FIGURE 8. INPUT BIAS CURRENT vs TOTAL QUIESCENT CURRENT
FIGURE 9. OPEN LOOP VOLTAGE GAIN vs TOTAL QUIESCENT CURRENT
1000 MAXIMUM OUTPUT CURRENT (mA) BIAS SETTING RESISTANCE (M) VS = 15 100 +6 -6 +3 -3 1 +1 -1 TA = 25oC RSET CONNECTED BETWEEN TERMINAL 5 AND V+ 0.01 1000 100 10 1 0.1 0.01 TOTAL QUIESCENT CURRENT (A) 0.001
100
10
10
0.1
0.1
FIGURE 10. BIAS SETTING RESISTANCE vs TOTAL QUIESCENT CURRENT
VS = 1.3V 1.5 OUTPUT VOLTAGE SWING (V) TA = 25oC RL = 50k
FIGURE 11. MAXIMUM OUTPUT CURRENT vs TOTAL QUIESCENT CURRENT
120 OPEN LOOP VOLTAGE GAIN (dB) 100 80 60 40 20
1.0 10k 5k 2k 1k 500
0.5
0 0 0.5 1.0 1.5 2.0 TOTAL QUIESCENT CURRENT (A)
0 RL = 10k, TA = 25oC C1- BETWEEN TERMINALS 1 AND 8 -20 0.1 1 101 102 103 FREQUENCY (Hz)
104
105
106
FIGURE 12. OUTPUT VOLTAGE SWING vs TOTAL QUIESCENT CURRENT
FIGURE 13. OPEN LOOP VOLTAGE GAIN vs FREQUENCY
6
CA3078, CA3078A Typical Performance Curves
100 OPEN LOOP VOLTAGE GAIN (dB) IQ = 20A TA = 25oC 120 100 80 60 100 40 300 1000 20 0 RL = 10k TA = 25oC -20 C1- BETWEEN TERMINALS 1 AND 8 0.1 0.1 +1 +0.1 -0.1 -0.1 -1 +10 -10 SUPPLY VOLTS (V+, V-) 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 CA3078A IQ = 20A CA3078 IQ = 100A VS = 6 +100 -100 1 101 102 103 104 105 106
(Continued)
VS = 6 IQ = 20A C1 = 0pF 0 PHASE ANGLE (DEGREES) INPUT BIAS CURRENT (nA) - CA3078T
10 VICR PEAK OUTPUT VOLTAGE (V), COMMON MODE VOLTAGE RANGE (V) VOM 1
C1 = 10pF C1 = 30pF 100
200 300 400
FREQUENCY (Hz)
FIGURE 15. OPEN LOOP VOLTAGE GAIN vs FREQUENCY
-1 -VICR -VOM
-10
INPUT OFFSET VOLTAGE (mV)
-75
-50
-25
0
25
50
75
100
125
TEMPERATURE (oC)
FIGURE 14. OUTPUT AND COMMON MODE VOLTAGE vs SUPPLY VOLTAGE
FIGURE 16. INPUT OFFSET VOLTAGE vs TEMPERATURE
INPUT OFFSET CURRENT (nA) - CA3078AT
INPUT OFFSET CURRENT (nA) - CA3078T
VS = 6
VS = 6 INPUT BIAS CURRENT (nA) - CA3078AT 15.0 12.5 10.0 7.5 5.0 2.5 0 -75 CA3078 IQ = 100A CA3078A IQ = 20A 100 75 50 25 0 125
2.5 2.0 1.5 1.0 0.5 0 -75 CA3078A IQ = 20A CA3078 IQ = 100A
10 8 6 4 2 0 125
-50
-25
0 25 50 TEMPERATURE (oC)
75
100
-50
-25
0 25 50 TEMPERATURE (oC)
75
100
FIGURE 17. INPUT OFFSET CURRENT vs TEMPERATURE
FIGURE 18. INPUT BIAS CURRENT vs TEMPERATURE
7
CA3078, CA3078A Typical Performance Curves
VS = 6 110 OPEN LOOP VOLTAGE GAIN (dB) 105 100 95 90 85 80 -75 CA3078A IQ = 20A CA3078 IQ = 100A
(Continued)
TOTAL QUIESCENT CURRENT (A) - CA3078AT TOTAL QUIESCENT CURRENT (A) - CA3078T 105
VS = 6
50 40 30 CA3078 20 10 0 -75 CA3078A 200 150 100 50 0 125
-50
-25
0
25
50
75
100
125
-50
-25
TEMPERATURE (oC)
0 25 50 TEMPERATURE (oC)
75
100
FIGURE 19. OPEN LOOP VOLTAGE GAIN vs TEMPERATURE
FIGURE 20. TOTAL QUIESCENT CURRENT vs TEMPERATURE
EQUIVALENT INPUT NOISE CURRENT (pA/Hz)
EQUIVALENT INPUT NOISE VOLTAGE (nV/Hz)
100
VS = 6 TA = 25oC CA3078AT
1
IQ = 20A
VS = 6 TA = 25oC CA3078AT
IQ = 100A 0.1 IQ = 20A
IQ = 100A 10
0 101
102
103 FREQUENCY (Hz)
104
105
0.01 101
102
103 FREQUENCY (Hz)
104
FIGURE 21. EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY
FIGURE 22. EQUIVALENT INPUT NOISE CURRENT vs FREQUENCY
8
CA3078, CA3078A Typical Performance Curves
1.5 RESISTOR-CAPACITOR COMPENSATION (R1 - C1 BETWEEN 1.25 TERMINALS 1 AND 8) 1 0.75 0.5 0.25 0 CAPACITOR COMPENSATION (BETWEEN TERMINALS 1 AND 8)
(Continued)
0.6 SLEW RATE (V/s) 0.5 0.4 0.3 0.2 0.1 0
SLEW RATE (V/s)
RESISTOR-CAPACITOR COMPENSATION (R1 - C1 BETWEEN TERMINALS 1 AND 8) CAPACITOR COMPENSATION (BETWEEN TERMINALS 1 AND 8)
0
10 20 30 40 50 60 70 80 90 CLOSED LOOP NON-INVERTING VOLTAGE GAIN (dB) 6 19.1 29.7 40 50 60 70 80 CLOSED LOOP INVERTING VOLTAGE GAIN (dB) 90
0
10 20 30 40 50 60 70 80 90 CLOSED LOOP NON-INVERTING VOLTAGE GAIN (dB) 6 19.1 29.7 40 50 60 70 80 CLOSED LOOP INVERTING VOLTAGE GAIN (dB) 90
Supply Volts: V+ = +6, V- = -6 Quiescent Current (IQ) = 100A Ambient Temperature (TA) = 25oC Load Impedance: RL = 10k, CL = 100pF Feedback Resistance (RF) = 0.1M Output Voltage (VOP-P) = 10V R1 determined for transient response with 10% overshoot on a 100mV output signal (R1 x C1 = 2.5 x 10-6) FIGURE 23. SLEW RATE vs CLOSED LOOP GAIN FOR IQ = 100mA - CA3078
Supply Volts: V+ = +6, V- = -6 Quiescent Current (IQ) = 20A Ambient Temperature (TA) = 25oC Load Impedance: RL = 10k, CL = 100pF Feedback Resistance (RF) = 0.1M Output Voltage (VOP-P) = 10V R1 determined for transient response with 10% overshoot on a 100mV output signal (R1 x C1 = 2 x 10-6) FIGURE 24. SLEW RATE vs CLOSED LOOP GAIN FOR IQ = 20mA - CA3078A
PHASE COMPENSATION CAPACITOR (pF)
1000
CAPACITOR COMPENSATION (BETWEEN TERMINALS 1 AND 8) RESISTOR-CAPACITOR COMPENSATION (R1 - C1 BETWEEN TERMINALS 1 AND 8)
PHASE COMPENSATION CAPACITOR (pF)
1000
CAPACITOR COMPENSATION (BETWEEN TERMINALS 1 AND 8) RESISTOR-CAPACITOR COMPENSATION (R1 - C1 BETWEEN TERMINALS 1 AND 8)
100
100
10
10
1
0
10 20 30 40 50 60 70 80 90 CLOSED LOOP NON-INVERTING VOLTAGE GAIN (dB) 6 19.1 29.7 40 50 60 70 80 90 CLOSED LOOP INVERTING VOLTAGE GAIN (dB)
1
0
10 20 30 40 50 60 70 80 90 CLOSED LOOP NON-INVERTING VOLTAGE GAIN (dB) 6 19.1 29.7 40 50 60 70 80 90 CLOSED LOOP INVERTING VOLTAGE GAIN (dB)
Supply Volts: V+ = +6, V- = -6 Quiescent Current (IQ) = 100A Ambient Temperature (TA) = 25oC Load Impedance: RL = 10k, CL = 100pF Feedback Resistance (RF) = 0.1M Output Voltage (VOP-P) = 100mV R1 determined for transient response with 10% overshoot on a 100mV output signal (R1 x C1 = 2.5 x 10-6) FIGURE 25. PHASE COMPENSATION CAPACITANCE vs CLOSED LOOP GAIN - CA3078
Supply Volts: V+ = +6, V- = -6 Quiescent Current (IQ) = 20A Ambient Temperature (TA) = 25oC Load Impedance: RL = 10k, CL = 100pF Feedback Resistance (RF) = 0.1M Output Voltage (VOP-P) = 100mV R1 determined for transient response with 10% overshoot on a 100mV output signal (R1 x C1 = 2 x 10-6) FIGURE 26. PHASE COMPENSATION CAPACITANCE vs CLOSED LOOP GAIN - CA3078A
9
CA3078, CA3078A Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B B1 C D D1 E eA eC
C A BS C
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 9.01 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 10.16 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.355 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280
-C-
e
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
E1 e eA eB L N
0.100 BSC 0.300 BSC 0.115 8 0.430 0.150 -
2.54 BSC 7.62 BSC 10.92 3.81 8
2.93
10
CA3078, CA3078A Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
L
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 8 0o 8o 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0o 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 11. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 12. Dimensioning and tolerancing per ANSI Y14.5M-1982. 13. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 14. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 15. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 16. "L" is the length of terminal for soldering to a substrate. 17. "N" is the number of terminal positions. 18. Terminal numbers are shown for reference only. 19. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 20. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
11
CA3078, CA3078A Metal Can Packages (Can)
REFERENCE PLANE A L L2 L1 A A OD OD1 Oe 2 1 Ob1 Ob BASE AND SEATING PLANE BASE METAL LEAD FINISH N k1 OD2
T8.C MIL-STD-1835 MACY1-X8 (A1)
e1 8 LEAD METAL CAN PACKAGE INCHES SYMBOL A Ob Ob1 Ob2 OD MIN 0.165 0.016 0.016 0.016 0.335 0.305 0.110 MAX 0.185 0.019 0.021 0.024 0.375 0.335 0.160 MILLIMETERS MIN 4.19 0.41 0.41 0.41 8.51 7.75 2.79 MAX 4.70 0.48 0.53 0.61 9.40 8.51 4.06 NOTES 1 1 2 1 1 1 3 3 4 Rev. 0 5/18/94
k
OD1
C L
F Q
OD2 e e1 F k k1
0.200 BSC 0.100 BSC 0.027 0.027 0.500 0.250 0.010 45o BSC 45o BSC 8 0.040 0.034 0.045 0.750 0.050 0.045 -
5.08 BSC 2.54 BSC 1.02 0.86 1.14 19.05 1.27 1.14
0.69 0.69 12.70 6.35 0.25
Ob1
Ob2
L L1
SECTION A-A
L2 Q
NOTES: 1. (All leads) Ob applies between L1 and L2. Ob1 applies between L2 and 0.500 from the reference plane. Diameter is uncontrolled in L1 and beyond 0.500 from the reference plane. 2. Measured from maximum diameter of the product. 3. is the basic spacing from the centerline of the tab to terminal 1 and is the basic spacing of each lead or lead position (N -1 places) from , looking at the bottom of the package. 4. N is the maximum number of terminal positions. 5. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 6. Controlling dimension: INCH.
N
45o BSC 45o BSC 8
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
12

▲Up To Search▲

Price & Availability of CA3078

	To Download CA3078 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .